Michael Robinson's COMP3 Instruction Set
========================================
(Permission to copy with attribution granted for noncommercial use.)
Machine implements a Harvard Architecture: 
   4 bit data bus, 
   8 bit instruction address + 4 bit conditional + 1 reserved, 
   16 bit instruction width

Instructions are split across two PROMs:
PROM #1: Stores Upper 8 bits of instruction jumptable

Each word in PROM #1 is the next instruction address (8 bits).  Words
are addressed by the following 13 bit word:

MSB                           LSB
+---+-----------------+---------+
| 0 | s s s s s s s s | C T G P |
+---+-----------------+---------+
  |         |           | | | \__ Propagate (1 = true)
  |         |           | | \____ Generate  (1 = true)
  |         |           | \______ Result = 15 (1 = true)
  |         |           \________ Carry  (0 = true)
  |         \____________________ Current instruction address
  \______________________________ Must be zero (reserved)

It should be apparent that each instruction is an implicit 16-way
branch.  The condition code (lower 4 bits of the above) generated
by the ALU selects the destination address.

PROM #2: Stores Lower 8 bits of instruction

Each word in PROM #2 is addressed by the following 13 bit word:

MSB                           LSB
+---+-----------------+---------+
| 0 | s s s s s s s s | 0 0 0 0 |
+---+-----------------+---------+
  |          |             \_____ Must be zero (reserved)
  |          \___________________ Current instruction address
  \______________________________ Must be zero (reserved)

So at present, only every 16th word in PROM #2 is used.

The contents of each word in PROM #2 follow the format:

MSB                 LSB
+---------+-------+---+
| a a a a | c c c | d |
+---------+-------+---+
     |        |     \__ Destination (0 = Accumulator, 1 = Memory)
     |        \________ Opcode (see table below)
     \_________________ Operand address

Opcodes: (Determine the output of the ALU, which is stored according to 
          the destination bit in instruction)
000 = ADD = Accumulator plus Operand
001 = CMP = Accumulator bitwise equivalence with Operand
010 = ANM = (Accumulator bitwise and with Operand) minus 1
011 = AND = Accumulator bitwise and with Operand
100 = ORP = (Accumulator bitwise or with Operand) plus Accumulator
101 = ORN = Accumulator bitwise or with (bitwise inverted Operand)
110 = DEC = Accumulator minus 1
111 = ACC = Accumulator 

Assembler Formats:

Comments begin with a semicolon (';') and may occur anywhere in the line.
All text following the the semicolon is ignored.

Symbols are single blocks of text followed by a single colon (':').  
Symbols act as labels for branches.  Every explicit branch must branch to
a symbol.

Instructions have the following required format:

OPCODE ADDRESS DESTINATION [BRANCH1 BRANCH2 ...]

OPCODE is one of the 3-letter mnemonics appearing above.

ADDRESS is a 4 bit hexadecimal number representing the operand address.

DESTINATION is one of the following one-character codes:
   '0' or 'A' = Write result to accumulator
   '1' or 'M' = Write result to the memory operand's address

BRANCH1.. are optional branches of the form
   yyyy:symbol

 y = a bit select: 0,1, or x (don't care)
 yyyy selects the conditional portion of the instruction address
 symbol specifies the destination symbol of the branch

 Branches are generated left to right, with rightmost ones overriding
 the others in the event of conflicts.  Any condition that is not specified
 causes a branch to the next instruction.